III-V semiconductors have much lower carrier effective masses than Si, which allows for high velocities. They are currently under active investigation to replace Si as the channel in large-scale integrated digital circuits. The advantage of a low carrier mass is, however, offset by a low density of conduction band states, which limits achievable carrier densities and thus negatively affects the transistor transconductance. This issue has become known as the “density of states bottleneck”. To allow for device scaling to nm-dimensions, gate dielectrics with very high dielectric constants (k) are required for large capacitance densities, low tunneling leakage, and to mitigate the density of states bottleneck.
To date, significant efforts have focused on optimizing the interface quality of high-k/III-V interfaces, with remarkable success. For example, the midgap trap densities (Dit) for gate stacks with high-k HfO2 and ZrO2 dielectrics, which can achieve sub-nm equivalent oxide thickness (EOT), are now in the 1012 cm−2 eV−1 range. Such interfaces allow for excellent transistor performance, including subthreshold slopes of 61 mV/dec and record transconductance. Near-ideal subthreshold slopes indicate that the interface is not degraded by interface traps. A common attribute of nearly all high quality high-k/III-V interfaces is the presence of an Al-oxide interface layer, which is either deposited intentionally, or forms during a pre-deposition cleaning process. For example, high-performance HfO2 and ZrO2 dielectrics use an in-situ, cyclic, pre-deposition tri-methylaluminum (TMA)/nitrogen plasma cleaning process that leads to the formation of a thin Al2O3 layer at the interface. The presence of Al2O3 severely limits capacitance (or equivalent oxide thickness, EOT) scaling, because the interface layer is connected in series with the high-k dielectric and Al2O3 has a very low dielectric constant (˜8). Further EOT scaling will therefore require either significantly thinning this layer, or replacing it with one that has a higher capacitance density. Furthermore, this must be achieved without degrading other key properties, in particular, interface trap density and leakage.
Highly-scaled gate dielectric stacks with low leakage and low interface trap densities are required for complementary metal-oxide-semiconductor technology with III-V semiconductor channels. HfO2 and ZrO2 gate stacks with extremely high accumulation capacitance densities, low leakage current, low frequency dispersion, and low midgap interface trap densities are desired.
What is needed is an interface containing TiO2, with only trace amounts of Ga-oxides or As-oxides, or As—As bonding are present to control leakage and frequency dispersion in high-k/III-V gate stacks.